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ds2431 1024-bit, 1-wire eeprom for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maximintegrated.com. 19-4675; rev 13; 3/12 general description the ds2431 is a 1024-bit, 1-wire eeprom chip orga- nized as four memory pages of 256 bits each. data is written to an 8-byte scratchpad, verified, and then copied to the eeprom memory. as a special feature, the four memory pages can individually be write protected or put in eprom-emulation mode, where bits can only be changed from a 1 to a 0 state. the ds2431 communi- cates over the single-conductor 1-wire bus. the commu- nication follows the standard 1-wire protocol. each device has its own unalterable and unique 64-bit rom registration number that is factory lasered into the chip. the registration number is used to address the device in a multidrop, 1-wire net environment. applications accessory/pcb identification medical sensor calibration data storage analog sensor calibration including ieee p1451.4 smart sensors ink and toner print cartridge identification after-market management of consumables features ? 1024 bits of eeprom memory partitioned into four pages of 256 bits ? individual memory pages can be permanently write protected or put in eprom-emulation mode (?rite to 0? ? switchpoint hysteresis and filtering to optimize performance in the presence of noise ? iec 1000-4-2 level 4 esd protection (?kv contact, ?5kv air, typical) ? reads and writes over a wide voltage range from 2.8v to 5.25v from -40? to +85? ? communicates to host with a single digital signal at 15.4kbps or 125kbps using 1-wire protocol ? also available as automotive version meeting aec-q100 grade 1 qualification requirements (ds2431-a1; refer to the ic data sheet for details) ordering information io r pup v cc c gnd ds2431 typical operating circuit note: the leads of to-92 packages on tape and reel are formed to approximately 100-mil (2.54mm) spacing. for details, refer to the package outline drawing. + denotes a lead(pb)-free/rohs-compliant package. t&r = tape and reel. * ep = exposed pad. part temp range pin-package ds2431+ -40c to +85c 3 to-92 ds2431+t&r -40c to +85c 3 to-92 ds2431p+ -40c to +85c 6 tsoc ds2431p+t&r -40c to +85c 6 tsoc ds2431g+u -40c to +85c 2 sfn (6mm x 6mm) ds2431g+t&r -40c to +85c 2 sfn (6mm x 6mm) (2.5k pcs) ds2431ga+u -40c to +85c 2 sfn (3.5mm x 6.5mm) ds2431ga+t&r -40c to +85c 2 sfn (3.5mm x 6.5mm) (2.5k pcs) ds2431q+t&r -40c to +85c 6 tdfn-ep* (2.5k pcs) ds2431x-s+ -40c to +85c 3x3 ucspr (2.5k pcs) ds2431x+ -40c to +85c 3x3 ucspr (10k pcs) 1-wire is a registered trademark of maxim integrated products, inc. pin configurations appear at end of data sheet.
1024-bit, 1-wire eeprom ds2431 2 maxim integrated absolute maximum ratings electrical characteristics (t a = -40? to +85?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. io voltage range to gnd .......................................-0.5v to +6v io sink current ...................................................................20ma operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-55? to +125? lead temperature (excluding ucsp, soldering, 10s).....+300? soldering temperature (reflow) to-92 ............................................................................+250? ail other packages, excluding sfn ..............................+260? parameter symbol conditions min typ max units io pin: general data 1-wire pullup voltage v pup (note 2) 2.8 5.25 v 1-wire pullup resistance r pup (notes 2, 3) 0.3 2.2 k input capacitance c io (notes 4, 5) 1000 pf input load current i l io pin at v pup 0.05 6.7 a high-to-low switching threshold v tl (notes 5, 6, 7) 0.5 v pup - 1.8 v input low voltage v il (notes 2, 8) 0.5 v low-to-high switching threshold v th (notes 5, 6, 9) 1.0 v pup - 1.0 v switching hysteresis v hy (notes 5, 6, 10) 0.21 1.70 v output low voltage v ol at 4ma (note 11) 0.4 v standard speed, r pup = 2.2k 5 overdrive speed, r pup = 2.2k 2 recovery time (notes 2,12) t rec overdrive speed, directly prior to reset pulse; r pup = 2.2k 5 s standard speed 0.5 5.0 rising-edge hold-off time (notes 5, 13) t reh overdrive speed not applicable (0) s standard speed 65 time slot duration (notes 2, 14) t slot overdrive speed 8 s io pin: 1-wire reset, presence-detect cycle standard speed 480 640 reset low time (note 2) t rstl overdrive speed 48 80 s standard speed 15 60 presence-detect high time t pdh overdrive speed 2 6 s standard speed 60 240 presence-detect low time t pdl overdrive speed 8 24 s standard speed 60 75 presence-detect sample time (notes 2, 15) t msp overdrive speed 6 10 s
1024-bit, 1-wire eeprom ds2431 maxim integrated 3 electrical characteristics (continued) (t a = -40? to +85?.) (note 1) parameter symbol conditions min typ max units io pin: 1-wire write standard speed 60 120 overdrive speed, v pup > 4.5v 5 15.5 write-zero low time (notes 2, 16, 17) t w0l overdrive speed 6 15.5 s standard speed 1 15 write-one low time (notes 2, 17) t w1l overdrive speed 1 2 s io pin: 1-wire read standard speed 5 15 - read low time (notes 2, 18) t rl overdrive speed 1 2 - s standard speed t rl + 15 read sample time (notes 2, 18) t msr overdrive speed t rl + 2 s eeprom programming current i prog (notes 5, 19) 0.8 ma programming time t prog (notes 20, 21) 10 ms at +25c 200k write/erase cycles (endurance) (notes 22, 23) n cy at +85c (worst case) 50k data retention (notes 24, 25, 26) t dr at +85c (worst case) 40 years note 1: limits are 100% production tested at t a = +25? and/or t a = +85?. limits over the operating temperature range and rel- evant supply voltage range are guaranteed by design and characterization. typical values are not guaranteed. note 2: system requirement. note 3: maximum allowable pullup resistance is a function of the number of 1-wire devices in the system and 1-wire recovery times. the specified value here applies to systems with only one device and with the minimum 1-wire recovery times. for more heavily loaded systems, an active pullup such as that found in the ds2482-x00, ds2480b, or ds2490 may be required. note 4: maximum value represents the internal parasite capacitance when v pup is first applied. once the parasite capacitance is charged, it does not affect normal communication. note 5: guaranteed by design, characterization, and/or simulation only. not production tested. note 6: v tl , v th , and v hy are a function of the internal supply voltage, which is a function of v pup , r pup , 1-wire timing, and capacitive loading on io. lower v pup , higher r pup , shorter t rec , and heavier capacitive loading all lead to lower values of v tl , v th , and v hy . note 7: voltage below which, during a falling edge on io, a logic 0 is detected. note 8: the voltage on io must be less than or equal to v ilmax at all times the master is driving io to a logic 0 level. note 9: voltage above which, during a rising edge on io, a logic 1 is detected. note 10: after v th is crossed during a rising edge on io, the voltage on io must drop by at least v hy to be detected as logic 0. note 11: the i-v characteristic is linear for voltages less than 1v. note 12: applies to a single device attached to a 1-wire line. note 13: the earliest recognition of a negative edge is possible at t reh after v th has been reached on the preceding rising edge. note 14: defines maximum possible bit rate. equal to t w0lmin + t recmin . note 15: interval after t rstl during which a bus master can read a logic 0 on io if there is a ds2431 present. the power-up presence- detect pulse could be outside this interval, but will be complete within 2ms after power-up. note 16: numbers in bold are not in compliance with legacy 1-wire product standards. see the comparison table . note 17: in figure 11 represents the time required for the pullup circuitry to pull the voltage on io up from v il to v th . the actual maximum duration for the master to pull the line low is t w1lmax + t f - and t w0lmax + t f - , respectively. note 18: in figure 11 represents the time required for the pullup circuitry to pull the voltage on io up from v il to the input-high threshold of the bus master. the actual maximum duration for the master to pull the line low is t rlmax + t f .
note 19: current drawn from io during the eeprom programming interval. the pullup circuit on io during the programming interval should be such that the voltage at io is greater than or equal to v pupmin . if v pup in the system is close to v pupmin , a low- impedance bypass of r pup , which can be activated during programming, may need to be added. note 20: interval begins t rehmax after the trailing rising edge on io for the last time slot of the e/s byte for a valid copy scratchpad sequence. interval ends once the device? self-timed eeprom programming cycle is complete and the current drawn by the device has returned from i prog to i l . note 21: t prog for units branded version ?1?is 12.5ms. t prog for units branded version ?2?and later is 10ms. note 22: write-cycle endurance is degraded as t a increases. note 23: not 100% production tested; guaranteed by reliability monitor sampling. note 24: data retention is degraded as t a increases. note 25: guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the data sheet limit at operating temperature range is established by reliability testing. note 26: eeprom writes can become nonfunctional after the data-retention time is exceeded. long-term storage at elevated tem- peratures is not recommended; the device can lose its write capability after 10 years at +125? or 40 years at +85?. comparison table legacy values ds2431 values standard speed (s) overdrive speed (s) standard speed (s) overdrive speed (s) parameter min max min max min max min max t slot (including t rec ) 61 (undefined) 7 (undefined) 65* (undefined) 8* (undefined) t rstl 480 (undefined) 48 80 480 640 48 80 t pdh 15 60 2 6 15 60 2 6 t pdl 60 240 8 24 60 240 8 24 t w0l 60 120 6 16 60 120 6 15.5 1024-bit, 1-wire eeprom ds2431 4 maxim integrated * intentional change; longer recovery time requirement due to modified 1-wire front-end. note: numbers in bold are not in compliance with legacy 1-wire product standards.
pin description pin tsoc to-92 tdfn-ep sfn ucspr name function 3, 4, 5, 6 3 1, 4, 5, 6 a2, a3, c2, c3 n.c. not connected 2 2 2 1 c1 io 1-wire bus interface. open-drain signal that requires an external pullup resistor. 1 1 3 2 a1 gnd ground reference ep exposed pad (tdfn only). solder evenly to the boards ground plane for proper operation. refer to applicat ion note 3273: exposed pads: a brief introduction for additional information. 1024-bit, 1-wire eeprom ds2431 maxim integrated 5 detailed description the ds2431 combines 1024 bits of eeprom, an 8-byte register/control page with up to 7 user read/write bytes, and a fully featured 1-wire interface in a single chip. each ds2431 has its own 64-bit rom registration number that is factory lasered into the chip to provide a guaranteed unique identity for absolute traceability. data is transferred serially through the 1-wire protocol, which requires only a single data lead and a ground return. the ds2431 has an additional memory area called the scratchpad that acts as a buffer when writing to the main memory or the register page. data is first written to the scratchpad from which it can be read back. after the data has been verified, a copy scratchpad command transfers the data to its final memory location. the ds2431 applications include accessory/pcb identification, medical sensor calibra- tion data storage, analog sensor calibration including ieee p1451.4 smart sensors, ink and toner print car- tridge identification, and after-market management of consumables. overview the block diagram in figure 1 shows the relationships between the major control and memory sections of the ds2431. the ds2431 has four main data components: 64-bit lasered rom, 64-bit scratchpad, four 32-byte pages of eeprom, and a 64-bit register page. memory function control unit data memory 4 pages of 256 bits each crc-16 generator 64-bit scratchpad 1-wire function control 64-bit lasered rom parasite power io register page 64 bits ds2431 figure 1. block diagram
1024-bit, 1-wire eeprom ds2431 6 maxim integrated the hierarchical structure of the 1-wire protocol is shown in figure 2. the bus master must first provide one of the seven rom function commands: read rom, match rom, search rom, skip rom, resume, overdrive-skip rom, or overdrive-match rom. upon completion of an overdrive-skip rom or overdrive- match rom command byte executed at standard speed, the device enters overdrive mode where all subsequent communication occurs at a higher speed. the protocol required for these rom function com- mands is described in figure 9. after a rom function command is successfully executed, the memory func- tions become accessible and the master can provide any one of the four memory function commands. the protocol for these memory function commands is described in figure 7. all data is read and written least significant bit first. 64-bit lasered rom each ds2431 contains a unique rom code that is 64 bits long. the first 8 bits are a 1-wire family code. the next 48 bits are a unique serial number. the last 8 bits are a cyclic redundancy check (crc) of the first 56 bits. see figure 3 for details. the 1-wire crc is generated using a polynomial generator consisting of a shift regis- ter and xor gates as shown in figure 4. the polynomial is x 8 + x 5 + x 4 + 1. additional information about the 1-wire crc is available in application note 27: understanding and using cyclic redundancy checks with maxim i button products . the shift register bits are initialized to 0. then, starting with the least significant bit of the family code, one bit at a time is shifted in. after the 8th bit of the family code has been entered, the serial number is entered. after the last bit of the serial number has been entered, the shift register contains the crc value. shifting in the 8 bits of the crc returns the shift register to all 0s. ds2431 command level: available commands: data field affected: read rom match rom search rom skip rom resume overdrive-skip rom overdrive-match rom 64-bit reg. #, rc-flag 64-bit reg. #, rc-flag 64-bit reg. #, rc-flag rc-flag rc-flag rc-flag, od-flag 64-bit reg. #, rc-flag, od-flag 1-wire rom function commands (see figure 9) write scratchpad read scratchpad copy scratchpad read memory 64-bit scratchpad, flags 64-bit scratchpad data memory, register page data memory, register page ds2431-specific memory function commands (see figure 7) figure 2. hierarchical structure for 1-wire protocol msb 8-bit crc code 48-bit serial number msb msblsb lsb lsb 8-bit family code (2dh) msblsb figure 3. 64-bit lasered rom i button is a registered trademark of maxim integrated products, inc.
1024-bit, 1-wire eeprom ds2431 maxim integrated 7 memory access data memory and registers are located in a linear address space, as shown in figure 5. the data memo- ry and the registers have unrestricted read access. the ds2431 eeprom array consists of 18 rows of 8 bytes each. the first 16 rows are divided equally into four memory pages (32 bytes each). these four pages are the primary data memory. each page can be indi- vidually set to open (unprotected), write protected, or eprom mode by setting the associated protection byte in the register row. as a factory default, the entire data memory is unprotected and its contents are unde- fined. the last two rows contain protection registers and reserved bytes. the register row consists of 4 pro- tection control bytes, a copy-protection byte, the facto- ry byte, and 2 user byte/manufacture id bytes. the manufacturer id can be a customer-supplied identifi- cation code that assists the application software in identifying the product the ds2431 is associated with. 1st stage 2nd stage 3rd stage 4th stage 7th stage 8th stage 6th stage 5th stage x 0 x 1 x 2 x 3 x 4 polynomial = x 8 + x 5 + x 4 + 1 input data x 5 x 6 x 7 x 8 figure 4. 1-wire crc generator address range type description protection codes 0000h to 001fh r/(w) data memory page 0 0020h to 003fh r/(w) data memory page 1 0040h to 005fh r/(w) data memory page 2 0060h to 007fh r/(w) data memory page 3 0080h* r/(w) protection control byte page 0 55h: write protect p0; aah: eprom mode p0; 55h or aah: write protect 80h 0081h* r/(w) protection control byte page 1 55h: write protect p1; aah: eprom mode p1; 55h or aah: write protect 81h 0082h* r/(w) protection control byte page 2 55h: write protect p2; aah: eprom mode p2; 55h or aah: write protect 82h 0083h* r/(w) protection control byte page 3 55h: write protect p3; aah: eprom mode p3; 55h or aah: write protect 83h 0084h* r/(w) copy protection byte 55h or aah: copy protect 0080h:008fh, and any write-protected pages 0085h r factory byte. set at factory. aah: write protect 85h, 86h, 87h; 55h: write protect 85h; unprotect 86h, 87h 0086h r/(w) user byte/manufacturer id 0087h r/(w) user byte/manufacturer id 0088h to 008fh reserved figure 5. memory map * once programmed to aah or 55h this address becomes read only. all other codes can be stored, but neither write protect the address nor activate any function.
1024-bit, 1-wire eeprom ds2431 8 maxim integrated contact the factory to set up and register a custom manufacturer id. the last row is reserved for future use. it is undefined in terms of r/w functionality and should not be used. in addition to the main eeprom array, an 8-byte volatile scratchpad is included. writes to the eeprom array are a two-step process. first, data is written to the scratchpad and then copied into the main array. this allows the user to first verify the data written to the scratchpad prior to copying into the main array. the device only supports full row (8-byte) copy operations. for data in the scratchpad to be valid for a copy opera- tion, the address supplied with a write scratchpad command must start on a row boundary, and 8 full bytes must be written into the scratchpad. the protection control registers determine how incom- ing data on a write scratchpad command is loaded into the scratchpad. a protection setting of 55h (write protect) causes the incoming data to be ignored and the target address main memory data to be loaded into the scratchpad. a protection setting of aah (eprom mode) causes the logical and of incoming data and target address main memory data to be loaded into the scratchpad. any other protection control register set- ting leaves the associated memory page open for unre- stricted write access. note: for the eprom mode to function, the entire affected memory page must first be programmed to ffh. protection-control byte settings of 55h or aah also write protect the protection-control byte. the protection-control byte setting of 55h does not block the copy. this allows write-protected data to be refreshed (i.e., reprogrammed with the current data) in the device. the copy-protection byte is used for a higher level of security and should only be used after all other protec- tion control bytes, user bytes, and write-protected pages are set to their final value. if the copy-protection byte is set to 55h or aah, all copy attempts to the regis- ter row and user-byte row are blocked. in addition, all copy attempts to write-protected main memory pages (i.e., refresh) are blocked. address registers and transfer status the ds2431 employs three address registers: ta1, ta2, and e/s (figure 6). these registers are common to many other 1-wire devices but operate slightly differ- ently with the ds2431. registers ta1 and ta2 must be loaded with the target address to which the data is writ- ten or from which data is read. register e/s is a read- only transfer-status register used to verify data integrity with write commands. e/s bits e[2:0] are loaded with the incoming t[2:0] on a write scratchpad command and increment on each subsequent data byte. this is, in effect, a byte-ending offset counter within the 8-byte scratchpad. bit 5 of the e/s register, called pf, is a logic 1 if the data in the scratchpad is not valid due to a loss of power or if the master sends fewer bytes than needed to reach the end of the scratchpad. for a valid write to the scratchpad, t[2:0] must be 0 and the mas- ter must have sent 8 data bytes. bits 3, 4, and 6 have no function; they always read 0. the highest valued bit of the e/s register, called authorization accepted (aa), acts as a flag to indicate that the data stored in the scratchpad has already been copied to the target memory address. writing data to the scratchpad clears this flag. bit # 7 6 5 4 3 2 1 0 target address (ta1) t7 t6 t5 t4 t3 t2 t1 t0 target address (ta2) t15 t14 t13 t12 t11 t10 t9 t8 ending address with data status (e/s) (read only) aa 0 pf 0 0 e2 e1 e0 figure 6. address registers
1024-bit, 1-wire eeprom ds2431 maxim integrated 9 writing with verification to write data to the ds2431, the scratchpad must be used as intermediate storage. first, the master issues the write scratchpad command to specify the desired target address, followed by the data to be written to the scratchpad. note that copy scratchpad commands must be performed on 8-byte boundaries, i.e., the three lsbs of the target address (t2, t1, t0) must be equal to 000b. if t[2:0] are sent with nonzero values, the copy function is blocked. under certain conditions (see the write scratchpad [0fh] section) the master receives an inverted crc-16 of the command, address (actual address sent), and data at the end of the write scratchpad command sequence. knowing this crc value, the master can compare it to the value it has cal- culated to decide if the communication was successful and proceed to the copy scratchpad command. if the master could not receive the crc-16, it should send the read scratchpad command to verify data integrity. as a preamble to the scratchpad data, the ds2431 repeats the target address ta1 and ta2 and sends the contents of the e/s register. if the pf flag is set, data did not arrive correctly in the scratchpad, or there was a loss of power since data was last written to the scratchpad. the master does not need to continue reading; it can start a new trial to write data to the scratchpad. similarly, a set aa flag together with a cleared pf flag indicates that the device did not recog- nize the write command. if everything went correctly, both flags are cleared. now the master can continue reading and verifying every data byte. after the master has verified the data, it can send the copy scratchpad command, for exam- ple. this command must be followed exactly by the data of the three address registers, ta1, ta2, and e/s. the master should obtain the contents of these regis- ters by reading the scratchpad. memory function commands the memory function flowchart (figure 7) describes the protocols necessary for accessing the memory of the ds2431. an example on how to use these functions to write to and read from the device is in the memory function example section. the communication between the master and the ds2431 takes place either at standard speed (default, od = 0) or at overdrive speed (od = 1). if not explicitly set into overdrive mode, the ds2431 assumes standard speed. write scratchpad [0fh] the write scratchpad command applies to the data memory and the writable addresses in the register page. for the scratchpad data to be valid for copying to the array, the user must perform a write scratchpad command of 8 bytes starting at a valid row boundary. the write scratchpad command accepts invalid addresses and partial rows, but subsequent copy scratchpad commands are blocked. after issuing the write scratchpad command, the mas- ter must first provide the 2-byte target address, fol- lowed by the data to be written to the scratchpad. the data is written to the scratchpad starting at the byte off- set of t[2:0]. the e/s bits e[2:0] are loaded with the starting byte offset and increment with each subse- quent byte. effectively, e[2:0] is the byte offset of the last full byte written to the scratchpad. only full data bytes are accepted. when executing the write scratchpad command, the crc generator inside the ds2431 (figure 13) calcu- lates a crc of the entire data stream, starting at the command code and ending at the last data byte as sent by the master. this crc is generated using the crc-16 polynomial by first clearing the crc generator and then shifting in the command code (0fh) of the write scratchpad command, the target addresses (ta1 and ta2), and all the data bytes. note that the crc-16 calculation is performed with the actual ta1 and ta2 and data sent by the master. the master can end the write scratchpad command at any time. however, if the end of the scratchpad is reached (e[2:0] = 111b), the master can send 16 read time slots and receive the crc generated by the ds2431. if a write scratchpad command is attempted to a write- protected location, the scratchpad is loaded with the data already existing in memory rather than the data transmitted. similarly, if the target address page is in eprom mode, the scratchpad is loaded with the bit- wise logical and of the transmitted data and data already existing in memory.
1024-bit, 1-wire eeprom ds2431 10 maxim integrated bus master tx memory function command bus master tx ta1 (t[7:0]), ta2 (t[15:8]) bus master rx ta1 (t[7:0]), ta2 (t[15:8]), and e/s byte bus master rx data byte from scratchpad master tx data byte to scratchpad applies only if the memory area is not protected. if write protected, the ds2431 copies the date byte from the target address into the scratchpad. if in eprom mode, the ds2431 loads the bitwise logical and of the transmitted byte and the data byte from the targeted address into the scratchpad. bus master rx "1"s ds2431 increments e[2:0] pf = 0 ds2431 sets pf = 1 clears aa = 0 sets e[2:0] = t[2:0] 0fh write scratchpad? n y n y n y y y n n master tx reset? e[2:0] = 7? t[2:0] = 0? master tx reset? ds2431 sets scratchpad byte counter = t[2:0] aah read scratchpad? n y ds2431 tx crc-16 of command, address, and data bytes as they were sent by the bus master bus master rx "1"s y n master tx reset? bus master rx crc-16 of command, address, e/s byte, and data bytes as sent by the ds2431 y n master tx reset? y byte counter = e[2:0]? from rom functions flowchart (figure 9) to rom functions flowchart (figure 9) ds2431 increments byte counter n to figure 7b from figure 7b figure 7a. memory function flowchart
1024-bit, 1-wire eeprom ds2431 maxim integrated 11 bus master tx ta1 (t[7:0]), ta2 (t[15:8]) applicable to all r/w memory locations. duration: t prog * * 1-wire idle high for power. ds2431 copies scratchpad data to address bus master rx "1"s aa = 1 bus master rx "1"s master tx reset? n y n n master tx reset? y master tx reset? bus master tx ta1 (t[7:0]), ta2 (t[15:8]) and e/s byte 55h copy scratchpad? n y y y n ds2431 tx "0" ds2431 tx "1" f0h read memory? n y y n auth. code match? y n y n n t[15:0] < 0090h? pf = 0? address < 90h? y copy protected? bus master rx "1"s master tx reset? n y ds2431 sets memory address = (t[15:0]) bus master rx data byte from memory address y n n master tx reset? address < 8fh? n y master tx reset? ds2431 increments address counter y to figure 7a from figure 7a figure 7b. memory function flowchart (continued)
1024-bit, 1-wire eeprom ds2431 12 maxim integrated read scratchpad [aah] the read scratchpad command allows verifying the target address and the integrity of the scratchpad data. after issuing the command code, the master begins reading. the first two bytes are the target address. the next byte is the ending offset/data status byte (e/s) fol- lowed by the scratchpad data, which may be different from what the master originally sent. this is of particular importance if the target address is within the register page or a page in either write-protection mode or eprom mode. see the write scratchpad [0fh] section for details. the master should read through the scratch- pad (e[2:0] - t[2:0] + 1 bytes), after which it receives the inverted crc based on data as it was sent by the ds2431. if the master continues reading after the crc, all data is logic 1. copy scratchpad [55h] the copy scratchpad command is used to copy data from the scratchpad to writable memory sections. after issuing the copy scratchpad command, the master must provide a 3-byte authorization pattern, which should have been obtained by an immediately preced- ing read scratchpad command. this 3-byte pattern must exactly match the data contained in the three address registers (ta1, ta2, e/s, in that order). if the pattern matches, the target address is valid, the pf flag is not set, and the target memory is not copy protected, then the aa flag is set and the copy begins. all 8 bytes of scratchpad contents are copied to the target memo- ry location. the duration of the device? internal data transfer is t prog during which the voltage on the 1-wire bus must not fall below 2.8v. a pattern of alternating 0s and 1s are transmitted after the data has been copied until the master issues a reset pulse. if the pf flag is set or the target memory is copy protected, the copy does not begin and the aa flag is not set. read memory [f0h] the read memory command is the general function to read data from the ds2431. after issuing the com- mand, the master must provide the 2-byte target address. after these 2 bytes, the master reads data beginning from the target address and can continue until address 008fh. if the master continues reading, the result is logic 1s. the device? internal ta1, ta2, e/s, and scratchpad contents are not affected by a read memory command. 1-wire bus system the 1-wire bus is a system that has a single bus mas- ter and one or more slaves. in all instances the ds2431 is a slave device. the bus master is typically a micro- controller. the discussion of this bus system is broken down into three topics: hardware configuration, trans- action sequence, and 1-wire signaling (signal types and timing). the 1-wire protocol defines bus transac- tions in terms of the bus state during specific time slots, which are initiated on the falling edge of sync pulses from the bus master. hardware configuration the 1-wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1-wire bus must have open-drain or three-state outputs. the 1-wire port of the ds2431 is open drain with an internal circuit equivalent to that shown in figure 8. a multidrop bus consists of a 1-wire bus with multiple slaves attached. the ds2431 supports both a standard and overdrive communication speed of 15.4kbps (max) and 125kbps (max), respectively. note that legacy 1-wire products support a standard communication speed of 16.3kbps and overdrive of 142kbps. the slightly reduced rates for the ds2431 are a result of additional recovery times, which in turn were driven by a 1-wire physical interface enhancement to improve noise immunity. the value of the pullup resistor primari- ly depends on the network size and load conditions. the ds2431 requires a pullup resistor of 2.2k (max) at any speed. the idle state for the 1-wire bus is high. if for any rea- son a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 16? (overdrive speed) or more than 120? (standard speed), one or more devices on the bus could be reset. transaction sequence the protocol for accessing the ds2431 through the 1-wire port is as follows: initialization rom function command memory function command transaction/data
1024-bit, 1-wire eeprom ds2431 maxim integrated 13 initialization all transactions on the 1-wire bus begin with an initial- ization sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that the ds2431 is on the bus and is ready to operate. for more details, see the 1-wire signaling section. 1-wire rom function commands once the bus master has detected a presence, it can issue one of the seven rom function commands that the ds2431 supports. all rom function commands are 8 bits long. a list of these commands follows (see the flowchart in figure 9). read rom [33h] the read rom command allows the bus master to read the ds2431? 8-bit family code, unique 48-bit serial num- ber, and 8-bit crc. this command can only be used if there is a single slave on the bus. if more than one slave is present on the bus, a data collision occurs when all slaves try to transmit at the same time (open drain pro- duces a wired-and result). the resultant family code and 48-bit serial number result in a mismatch of the crc. match rom [55h] the match rom command, followed by a 64-bit rom sequence, allows the bus master to address a specific ds2431 on a multidrop bus. only the ds2431 that exact- ly matches the 64-bit rom sequence responds to the subsequent memory function command. all other slaves wait for a reset pulse. this command can be used with a single device or multiple devices on the bus. search rom [f0h] when a system is initially brought up, the bus master might not know the number of devices on the 1-wire bus or their registration numbers. by taking advantage of the wired-and property of the bus, the master can use a process of elimination to identify the registration numbers of all slave devices. for each bit of the regis- tration number, starting with the least significant bit, the bus master issues a triplet of time slots. on the first slot, each slave device participating in the search outputs the true value of its registration number bit. on the sec- ond slot, each slave device participating in the search outputs the complemented value of its registration num- ber bit. on the third slot, the master writes the true value of the bit to be selected. all slave devices that do not match the bit written by the master stop participat- ing in the search. if both of the read bits are zero, the master knows that slave devices exist with both states of the bit. by choosing which state to write, the bus master branches in the rom code tree. after one com- plete pass, the bus master knows the registration num- ber of a single device. additional passes identify the registration numbers of the remaining devices. refer to application note 187: 1-wire search algorithm for a detailed discussion, including an example. skip rom [cch] this command can save time in a single-drop bus sys- tem by allowing the bus master to access the memory functions without providing the 64-bit rom code. if more than one slave is present on the bus and, for example, a read command is issued following the skip rom command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-and result). rx r pup i l v pup bus master open-drain port pin 100 mosfet tx rx tx data ds2431 1-wire port rx = receive tx = transmit figure 8. hardware configuration
1024-bit, 1-wire eeprom ds2431 14 maxim integrated ds2431 tx presence pulse bus master tx reset pulse bus master tx rom function command ds2431 tx crc byte ds2431 tx family code (1 byte) ds2431 tx serial number (6 bytes) rc = 0 master tx bit 0 rc = 0 rc = 0 rc = 0 od = 0 y y y y y y y y 33h read rom command? n 55h match rom command? bit 0 match? bit 0 match? n n n n n n n f0h search rom command? od reset pulse? n n cch skip rom command? n rc = 1 master tx bit 1 master tx bit 63 bit 1 match? bit 63 match? y y rc = 1 from memory functions flowchart (figure 7) to memory functions flowchart (figure 7) ds2431 tx bit 0 ds2431 tx bit 0 master tx bit 0 bit 1 match? bit 63 match? ds2431 tx bit 1 ds2431 tx bit 1 master tx bit 1 ds2431 tx bit 63 ds2431 tx bit 63 master tx bit 63 y to figure 9b to figure 9b from figure 9b from figure 9b figure 9a. rom functions flowchart
1024-bit, 1-wire eeprom ds2431 maxim integrated 15 rc = 0; od = 1 rc = 0; od = 1 n bit 0 match? y n rc = 1? y a5h resume command? n y 3ch overdrive- skip rom? n y 69h overdrive- match rom? from figure 9a from figure 9a to figure 9a to figure 9a n y y n master tx reset? y master tx reset? n bit 1 match? master tx bit 0 master tx bit 1 od = 0 n od = 0 n od = 0 y rc = 1 bit 63 match? master tx bit 63 y figure 9b. rom functions flowchart (continued)
1024-bit, 1-wire eeprom ds2431 16 maxim integrated resume [a5h] to maximize the data throughput in a multidrop envi- ronment, the resume command is available. this com- mand checks the status of the rc bit and, if it is set, directly transfers control to the memory function com- mands, similar to a skip rom command. the only way to set the rc bit is through successfully executing the match rom, search rom, or overdrive-match rom command. once the rc bit is set, the device can repeatedly be accessed through the resume com- mand. accessing another device on the bus clears the rc bit, preventing two or more devices from simultane- ously responding to the resume command. overdrive-skip rom [3ch] on a single-drop bus this command can save time by allowing the bus master to access the memory func- tions without providing the 64-bit rom code. unlike the normal skip rom command, the overdrive-skip rom command sets the ds2431 into the overdrive mode (od = 1). all communication following this command must occur at overdrive speed until a reset pulse of minimum 480? duration resets all devices on the bus to standard speed (od = 0). when issued on a multidrop bus, this command sets all overdrive-supporting devices into overdrive mode. to subsequently address a specific overdrive-supporting device, a reset pulse at overdrive speed must be issued followed by a match rom or search rom com- mand sequence. this speeds up the time for the search process. if more than one slave supporting overdrive is present on the bus and the overdrive-skip rom command is followed by a read command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired- and result). overdrive-match rom [69h] the overdrive-match rom command followed by a 64- bit rom sequence transmitted at overdrive speed allows the bus master to address a specific ds2431 on a multidrop bus and to simultaneously set it in overdrive mode. only the ds2431 that exactly matches the 64-bit rom sequence responds to the subsequent memory function command. slaves already in overdrive mode from a previous overdrive-skip rom or successful overdrive-match rom command remain in overdrive mode. all overdrive-capable slaves return to standard speed at the next reset pulse of minimum 480? dura- tion. the overdrive-match rom command can be used with a single device or multiple devices on the bus. 1-wire signaling the ds2431 requires strict protocols to ensure data integrity. the protocol consists of four types of signal- ing on one line: reset sequence with reset pulse and presence pulse, write-zero, write-one, and read-data. except for the presence pulse, the bus master initiates all falling edges. the ds2431 can communicate at two different speeds: standard speed and overdrive speed. if not explicitly set into the overdrive mode, the ds2431 communicates at standard speed. while in overdrive mode, the fast timing applies to all waveforms. to get from idle to active, the voltage on the 1-wire line needs to fall from v pup below the threshold v tl . to get from active to idle, the voltage needs to rise from v ilmax past the threshold v th . the time it takes for the voltage to make this rise is seen in figure 10 as , and its duration depends on the pullup resistor (r pup ) used and the capacitance of the 1-wire network attached. the voltage v ilmax is relevant for the ds2431 when determining a logical level, not triggering any events. figure 10 shows the initialization sequence required to begin any communication with the ds2431. a reset pulse followed by a presence pulse indicates that the ds2431 is ready to receive data, given the correct rom and memory function command. if the bus master uses slew-rate control on the falling edge, it must pull down the line for t rstl + t f to compensate for the edge. a t rstl duration of 480? or longer exits the overdrive mode, returning the device to standard speed. if the ds2431 is in overdrive mode and t rstl is no longer than 80?, the device remains in overdrive mode. if the device is in overdrive mode and t rstl is between 80? and 480?, the device resets, but the communication speed is undetermined. after the bus master has released the line it goes into receive mode. now the 1-wire bus is pulled to v pup through the pullup resistor or, in the case of a ds2482- x00 or ds2480b driver, through the active circuitry. when the threshold v th is crossed, the ds2431 waits for t pdh and then transmits a presence pulse by pulling the line low for t pdl . to detect a presence pulse, the master must test the logical state of the 1-wire line at t msp . the t rsth window must be at least the sum of t pdhmax , t pdlmax , and t recmin . immediately after t rsth is expired, the ds2431 is ready for data commu- nication. in a mixed population network, t rsth should be extended to minimum 480? at standard speed and 48? at overdrive speed to accommodate other 1-wire devices.
1024-bit, 1-wire eeprom ds2431 maxim integrated 17 read/write time slots data communication with the ds2431 takes place in time slots that carry a single bit each. write time slots transport data from bus master to slave. read time slots transfer data from slave to master. figure 11 illus- trates the definitions of the write and read time slots. all communication begins with the master pulling the data line low. as the voltage on the 1-wire line falls below the threshold v tl , the ds2431 starts its internal timing generator that determines when the data line is sampled during a write time slot and how long data is valid during a read time slot. master-to-slave for a write-one time slot, the voltage on the data line must have crossed the v th threshold before the write- one low time t w1lmax is expired. for a write-zero time slot, the voltage on the data line must stay below the v th threshold until the write-zero low time t w0lmin is expired. for the most reliable communication, the volt- age on the data line should not exceed v ilmax during the entire t w0l or t w1l window. after the v th threshold has been crossed, the ds2431 needs a recovery time t rec before it is ready for the next time slot. slave-to-master a read-data time slot begins like a write-one time slot. the voltage on the data line must remain below v tl until the read low time t rl is expired. during the t rl window, when responding with a 0, the ds2431 starts pulling the data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. when responding with a 1, the ds2431 does not hold the data line low at all, and the voltage starts rising as soon as t rl is over. the sum of t rl + (rise time) on one side and the inter- nal timing generator of the ds2431 on the other side define the master sampling window (t msrmin to t msrmax ), in which the master must perform a read from the data line. for the most reliable communication, t rl should be as short as permissible, and the master should read close to but no later than t msrmax . after reading from the data line, the master must wait until t slot is expired. this guarantees sufficient recovery time t rec for the ds2431 to get ready for the next time slot. note that t rec specified herein applies only to a single ds2431 attached to a 1-wire line. for multide- vice configurations, t rec must be extended to accom- modate the additional 1-wire device input capacitance. alternatively, an interface that performs active pullup during the 1-wire recovery time such as the ds2482- x00 or ds2480b 1-wire line drivers can be used. resistor master ds2431 t rstl t pdl t rsth t pdh master tx "reset pulse" master rx "presence pulse" v pup v ihmaster v th v tl v ilmax 0v t f t rec t msp figure 10. initialization procedure: reset and presence pulse
1024-bit, 1-wire eeprom ds2431 18 maxim integrated resistor master resistor master resistor master ds2431 v pup v ihmaster v th v tl v ilmax 0v t f v pup v ihmaster v th v tl v ilmax 0v t f v pup v ihmaster v th v tl v ilmax 0v t f t slot t w1l t rec t slot t slot t w0l t rec master sampling window t rl t msr write-one time slot write-zero time slot read-data time slot figure 11. read/write timing diagrams
1024-bit, 1-wire eeprom ds2431 maxim integrated 19 improved network behavior (switchpoint hysteresis) in a 1-wire environment, line termination is possible only during transients controlled by the bus master (1-wire driver). 1-wire networks, therefore, are suscep- tible to noise of various origins. depending on the physical size and topology of the network, reflections from end points and branch points can add up or can- cel each other to some extent. such reflections are visi- ble as glitches or ringing on the 1-wire communication line. noise coupled onto the 1-wire line from external sources can also result in signal glitching. a glitch dur- ing the rising edge of a time slot can cause a slave device to lose synchronization with the master and, consequently, result in a search rom command com- ing to a dead end or cause a device-specific function command to abort. for better performance in network applications, the ds2431 uses a new 1-wire front-end, which makes it less sensitive to noise. the ds2431? 1-wire front-end differs from traditional slave devices in three characteristics. 1) there is additional lowpass filtering in the circuit that detects the falling edge at the beginning of a time slot. this reduces the sensitivity to high-frequency noise. this additional filtering does not apply at overdrive speed. 2) there is a hysteresis at the low-to-high switching threshold v th . if a negative glitch crosses v th but does not go below v th - v hy , it is not recognized (figure 12, case a). the hysteresis is effective at any 1-wire speed. 3) there is a time window specified by the rising edge hold-off time t reh during which glitches are ignored, even if they extend below the v th - v hy threshold (figure 12, case b, t gl < t reh ). deep voltage drops or glitches that appear late after crossing the v th threshold and extend beyond the t reh window can- not be filtered out and are taken as the beginning of a new time slot (figure 12, case c, t gl t reh ). devices that have the parameters v hy and t reh speci- fied in their electrical characteristics use the improved 1-wire front-end. crc generation the ds2431 uses two different types of crcs. one crc is an 8-bit type and is stored in the most signifi- cant byte of the 64-bit rom. the bus master can com- pute a crc value from the first 56 bits of the 64-bit rom and compare it to the value stored within the ds2431 to determine if the rom data has been received error-free. the equivalent polynomial function of this crc is x 8 + x 5 + x 4 + 1. this 8-bit crc is received in the true (noninverted) form. it is computed at the factory and lasered into the rom. the other crc is a 16-bit type, generated according to the standardized crc-16 polynomial function x 16 + x 15 + x 2 + 1. this crc is used for fast verification of a data transfer when writing to or reading from the scratchpad. in contrast to the 8-bit crc, the 16-bit crc is always communicated in the inverted form. a crc generator inside the ds2431 chip (figure 13) calculates a new 16- bit crc, as shown in the command flowchart (figure 7). the bus master compares the crc value read from the device to the one it calculates from the data and decides whether to continue with an operation or to reread the portion of the data with the crc error. with the write scratchpad command, the crc is gen- erated by first clearing the crc generator and then shifting in the command code, the target addresses ta1 and ta2, and all the data bytes as they were sent v pup v th v hy 0v t reh t gl t reh t gl case a case c case b figure 12. noise suppression scheme
1024-bit, 1-wire eeprom ds2431 20 maxim integrated by the bus master. the ds2431 transmits this crc only if e[2:0] = 111b. with the read scratchpad command, the crc is gen- erated by first clearing the crc generator and then shifting in the command code, the target addresses ta1 and ta2, the e/s byte, and the scratchpad data as they were sent by the ds2431. the ds2431 transmits this crc only if the reading continues through the end of the scratchpad. for more information on generating crc values, refer to application note 27. 1st stage 2nd stage 3rd stage 4th stage 7th stage 8th stage 6th stage 5th stage x 0 x 1 x 2 x 3 x 4 polynomial = x 16 + x 15 + x 2 + 1 input data crc output x 5 x 6 11th stage 12th stage 15th stage 14th stage 13th stage x 11 x 12 9th stage 10th stage x 9 x 10 x 13 x 14 x 7 16th stage x 16 x 15 x 8 figure 13. crc-16 hardware description and polynomial command-specific 1-wire communication protocol?egend symbol description rst 1-wire reset pulse generated by master. pd 1-wire presence pulse generated by slave. select command and data to satisfy the rom function protocol. ws command "write scratchpad." rs command "read scratchpad." cps command "copy scratchpad." rm command "read memory." ta target address ta1, ta2. ta-e/s target address ta1, ta2 with e/s byte. <8Ct[2:0] bytes> transfer of as many bytes as needed to reach the end of the scratchpad for a given target address. transfer of as many data bytes as are needed to reach the end of the memory. crc-16 transfer of an inverted crc-16. ff loop indefinite loop where the master reads ff bytes. aa loop indefinite loop where the master reads aa bytes. programming data transfer to eeprom; no activity on the 1-wire bus permitted during this time.
1024-bit, 1-wire eeprom ds2431 maxim integrated 21 command-specific 1-wire communication protocol?olor codes 1-wire communication examples master to slave slave to master programming write scratchpad (cannot fail) rst pd select ws ta <8Ct[2:0] bytes> crc-16 ff loop read scratchpad (cannot fail) rst pd select rs ta-e/s <8Ct[2:0] bytes> crc-16 ff loop copy scratchpad (success) rst pd select cps ta-e/s programming aa loop copy scratchpad (invalid address or pf = 1 or copy protected) rst pd select cps ta-e/s ff loop read memory (success) rst pd select rm ta ff loop read memory (invalid address) rst pd select rm ta ff loop
1024-bit, 1-wire eeprom ds2431 22 maxim integrated memory function example write to the first 8 bytes of memory page 1. read the entire memory. with only a single ds2431 connected to the bus mas- ter, the communication looks like this: master mode data (lsb first) comments tx (reset) reset pulse rx (presence) presence pulse tx cch issue skip rom command tx 0fh issue write scratchpad command tx 20h ta1, beginning offset = 20h tx 00h ta2, address = 00 20h tx <8 data bytes> write 8 bytes of data to scratchpad rx <2 bytes crc-16 > read crc to check for data integrity tx (reset) reset pulse rx (presence) presence pulse tx cch issue skip rom command tx aah issue read scratchpad command rx 20h read ta1, beginning offset = 20h rx 00h read ta2, address = 00 20h rx 07h read e/s, ending offset = 111b, aa, pf = 0 rx <8 data bytes> read scratchpad data and verify rx <2 bytes crc-16 > read crc to check for data integrity tx (reset) reset pulse rx (presence) presence pulse tx cch issue skip rom command tx 55h issue copy scratchpad command tx 20h ta1 tx 00h ta2 tx 07h e/s (authorization code) <1-wire idle high> wait t progmax for the copy function to complete rx aah read copy status, aah = success tx (reset) reset pulse rx (presence) presence pulse tx cch issue skip rom command tx f0h issue read memory command tx 00h ta1, beginning offset = 00h tx 00h ta2, address = 00 00h rx <144 data bytes> read the entire memory tx (reset) reset pulse rx (presence) presence pulse
1024-bit, 1-wire eeprom ds2431 maxim integrated 23 2 3 1 2 3 1 3 2 1 n.c. io gnd to-92 top view n.c. io gnd n.c. n.c. n.c. tsoc + 5 4 6 2 3 1 ds2431 sfn (6mm 6mm 0.9mm) sfn (3.5mm 6.5mm 0.75mm) bottom view bottom view note: the sfn package is qualified for electro-mechanical contact applications only, not for soldering. for more information, refer to application note 4132: attachment methods for the electro-mechanical sfn package. 1 1 2 2 io io gnd gnd front view (t&r version) front view side view ds2431 ds2431g ds2431ga ucspr top view gnd n.c. n.c. a1 a2 a3 c1 c2 c3 io n.c. n.c. 16 n.c. n.c. 25 io n.c. 34 gnd n.c. tdfn (3mm 3mm) top view ds2431 2431 ymrrf + *ep *exposed pad pin configurations
1024-bit, 1-wire eeprom ds2431 24 maxim integrated user direction of feed leads face up in orientation shown above. sfn (6mm 6mm 0.9mm) user direction of feed leads face up in orientation shown above. sfn (3.5mm 6.5mm 0.75mm) sfn package orientation on tape and reel
1024-bit, 1-wire eeprom ds2431 maxim integrated 25 package type package code outline no. land pattern no. 3 to-92 (bulk) q3+1 21-0248 3 to-92 (t&r) q3+4 21-0250 6 tsoc d6+1 21-0382 90-0321 2 sfn (6mm x 6mm) g266n+1 21-0390 2 sfn (3.5mm x 6.5mm) t23a6n+1 21-0575 6 tdfn-ep t633+2 21-0137 90-0058 6 ucspr br622+1 21-0376 refer to application note 1891 package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the dra wing pertains to the package regardless of rohs status.
1024-bit, 1-wire eeprom ds2431 26 maxim integrated revision history revision number revision date description pages changed 0 050704 initial release replaced pin configuration 1 in the electrical characteristics table, changed v tl(min) from 0.5v to 0.46v and v tl(max) from 4.1v to 4.4v; changed v hy(min) from 0.22v to 0.21v 2 1 081604 in the copy scratchpad [55h] section, corrected the copy time from 13ms to 12.5ms 14 added the sfn package and updated the ordering information table 1, 24 in the pin configuration , added a note to the csp package outline *see package reliability report for important guidelines on qualified usage conditions. 1 in the electrical characteristics table, changed the t prog (programming time) ec table parameter from 12.5ms to 10ms for version a2 (see also pages 1, 13). removed t fpd and updated t pdh , t msp , t w0l accordingly. changed i prog max to 0.8ma to match gbd 1, 2, 3, 13 2 090506 updated memory function example table 23 added csp package outline drawing number to pin configuration 1 changed v tl(min) from 0.46v to 0.5v in the electrical characteristics table 2 3 122106 in the absolute maximum ratings , changed storage temp to -55c to +125c; in the electrical characteristics table, changed v th , v tl based on v pup and data retention to 40 years min at 85c; added note to retention spec: eeprom writes can become nonfunctional after the data-retention time is exceeded. long-term storage at elevated temperatures is not recommended; the device can lose its write capability after 10 years at +125c or 40 years at +85c. 1, 2, 3 in the ordering information table, removed all leaded part numbers and added the tdfn-ep package 1, 24 in the electrical characteristics table, changed the v il(max) spec from 0.3v to 0.5v; removed from the t w1l(max) spec; added note 17 to t w0l spec; updated ec table notes 17 and 18; corrected note 20 2, 3 added ep function to the pin description table 3 added to figure 11 write-zero time slot 19 4 102207 in the pin configuration , added the package drawing information/weblink and a note that the sfn package is qualified for electro-mechanical contact applications only, not for soldering. added the sfn package orientation on tape-and-reel section. in the ordering information , added note to contact factory for availability of the ucspr package. added note that to-92 t&r leads are formed to approximately 100-mil spacing 24 in the sfn pin configuration , added reference to application note 4132 24 5 032008 added package information table 25 6 8/08 created newer template-style data sheet all 7 6/09 deleted contact factory note in ordering information ; updated pin description and pin configurations to reflect changes in pin assignment of ucspr package 1, 5, 23 8 10/09 corrected part number in ordering information table 1 9 12/10 deleted the automotive version reference in the features section 1 10 3/11 added the automotive version reference to the features section 1
1024-bit, 1-wire eeprom ds2431 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 27 2012 maxim integrated the maxim logo and maxim integrated are trademarks of maxim integrated products, inc. revision history (continued) revision number revision date description pages changed 11 1/12 updated note 1 in the electrical characteristics section; specified the data memory default status and added a note that the memory must be programmed to ffh for the eprom mode to function to the memory access section 3, 7, 8 12 2/12 added the 3.5mm x 6.5mm sfn package information to the ordering information table, pin configurations , and package information table 1, 23, 24, 25 13 3/12 revised the electrical characteristics table notes 4 and 15 3

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